1. Field of the Invention
The present invention relates to a one-dimensional image sensor that receives reflection light from an original to which light is irradiated, and converts a light signal into an electric signal.
2. Description of the Related Art
A conventional image sensor IC uses a method of reading out the outputs of photoelectric conversion elements to a third common line SL3 by sequentially turning on switches SW2n to SW2 (n+1)+1, as shown in FIG. 6. The third common line SL3 is connected to a first terminal of a reset gate RG, and a second terminal of the reset gate RG is connected to a GND terminal. The reset gate RG is used by clamping the third common line SL3 to a GND potential, in accordance with a control signal Q2 of a control circuit CC (see JP 02-262760 A).
In the one-dimensional image sensor which is configured such that a plurality of image sensors IC are straightly mounted on a substrate, the common line of output terminals becomes a long wiring. Thus, capacitance and resistance components of the output terminals serve as a load, which reduces the signal level of the output signal. The above-mentioned one-dimensional image sensor has a built-in amplifier so that the drop in the signal level of the output signal is suppressed.
When the IC is driven by a single power supply in such a way that the signal line connected to an input terminal of the amplifier belongs to a linear region of the amplifier, a light receiving element is reset to a reference voltage value, or a common signal line is reset. Consequently, an offset is given, thereby adjusting an input voltage range.
However, in the above-mentioned conventional method, the process variation inside a wafer surface brings about the variation in the offset voltage for each IC, and this consequently makes the output voltage of the IC different for each unit block, and results in a problem that the output voltages are stepped.
FIG. 7 is the circuit example using the conventional image sensor. A plurality of image sensors IC of unit blocks 25 are connected to each other. Respective clock signal terminals CLK are connected to a CLK common line 19, an image signal terminal SIG is connected to an SIG common line 20, and the SIG common line 20 is connected through an external image output terminal SIG to a non-inversion input terminal of an operational amplifier 21 operated by a single power supply under a GND power supply standard of the image sensor. Then, at a ratio of a resistor 22 of a resistance value R3 to a resistor 23 of a resistance value R4, a non-inversion amplification is performed on the image signal SIG, and it is outputted from a VOUT terminal. A capacitance 24 is a pseudo capacitance CCPL of the CLK common line 19 and the SIG common line 20.
FIG. 8 shows the output waveform in which the image sensor shown in FIG. 7 is used. When it is configured such that an amplifying circuit is not built in the IC in order to avoid the stepped situation of the output voltages as mentioned above, a high resistance state occurs at the time of the signal output, which receives the influence of the wiring layout of the substrate. In particular, when the pseudo capacitance CCPL between a CLK control signal line and the SIG common line is large, a potential VSIG of the image signal terminal SIG receives the influence of the under-shoot-noise of a CLK signal, and may be possibly equal to or less than 0 V of the GND voltage.
When an external amplifier in which the GND voltage is driven by a common single power supply is used under this condition, the under-shoot-noise of the potential VSIG as mentioned above becomes equal to or less than the input voltage range of the external amplifier, and because of the circuit configuration, a response signal is delayed, and in particular, this results in a problem that as the speed of the operation is faster, the image signal receives the severer influence.